Microarchitecture based RISC-V Instruction Set Architecture for Low Power Application

Abstract

The goal of many contemporary and speculative applications is to create highly efficient CPUs and one among the architecture that is meeting out the above said condition is RISC V processor microarchitecture. The RISC-V Instruction Set Architecture [ISA] supports the microarchitecture. Microarchitecture and instruction set architecture are the two key elements of processor design. In comparison with other instruction execution stages, the high hardware complexity of multiplier and divider circuits must be included in any core microarchitecture. As a result, the construction of an appropriate hardware circuit capable of multiplication and division determines the total size, power, and performance of a core. With the exception of load and store, this core has four stages in which all instructions are executed. One clock cycle is used to complete the arithmetic operations. However, in order to reduce the critical path latency, the division and multiplication operations are repeatedly performed. In this project, the Baugh Wooley multiplier will be used because it can run in two clock cycles. Instructions for multiplication and division are included in RISC-V. The fundamental microarchitecture is designed to enable the execution of instructions with the minimal amount of structural risk, control and data. The ultimate objective is to create a low-power application, with only the most important functions. It was primarily concerned with optimizing the size, power, and efficiency of the system.